The present invention relates to the field of testing integrated logic circuits and more specifically, it relates to methods for inserting test points into an integrated logic circuit for generating and observing faults in the integrated the logic circuit during test.
The semiconductor industry has increasingly been able, by combination of increasing density and increasing die size, to fabricate dies with increasing numbers of logic circuits per die. This has, in turn, increased the number of combinational logic circuits that must be tested in order to assure that devices without faults are not shipped to consumers.
An important component in any test methodology is the step of generating the test data to apply to the combinational logic. Several concerns arise when generating the test data, including the number of test vectors and size of each test vector required for any given scan chain/combinational logic subset. Corollary concerns for physical testing include the amount of tester time required to execute each test vector and the amount of tester buffer memory consumed by the tests. Both these corollary concerns increase as the number of logic circuits per die increase and therefore increase the cost of testing.
The specific design and size of the combinational logic to be tested also directly affects the size of the test vector required. Ideally, the test vector is designed to test every path in the combinational logic. Some logic circuits are not completely testable, or even testable to acceptable levels of probability, without excessively large test vectors that would consume prohibitive amounts of tester resource. FIG. 1 illustrates an exemplary complex combinational logic function. Complex logic device 90 OR""s sixteen inputs together to produce a single output. A vector of sixteen 0""s is applied to the inputs of complex logic device 90 is required to produce a zero on the output the device. Therefore, any sixteen-bit test vector applied to the inputs of complex logic device 90 would have a 1/216 probability of producing a 0 out. Thus 216 test vectors are required to 100% test complex logic device 90.
One method of testing logic circuits used in the industry, incorporating placing scan in latches before and scan out latches after the logic circuits to be tested, will be used to illustrate the complexities of testing combinational logic circuits. It should be noted, however, that the following general discussion on testing combinational logic circuits as well as description of the present invention is not limited to scan latch testing but is applicable to other testing methods as well. One example of other testing methodologies is functional testing. In functional testing stimulus is applied to the logic primary inputs and then sequenced through the combinational logic and the internal sequential logic by pulsing the input clock while applying enabling values at the primary inputs. The overall sequence of the input stimuli and clock pulses is determined by test generation software or by human intervention.
FIG. 2 is a schematic diagram illustrating a scan latch circuit for testing a complex combinational logic circuit. Combinational logic circuit 100 includes a first circuit portion 105 coupled to a second circuit portion 110 through a node 115. Signals generated in first circuit portion 105 are applied to node 115 by a driver cell 120. While a single node 105 has been illustrated, additional nodes connecting first circuit portion 105 and second circuit portion 110 are not precluded. During test mode, test data (in the form of a test vector of 0xe2x80x2s and 1xe2x80x2s) is clocked from a data input pin 125 through scan in latches 130A, 130B, 130C and 130D, then through the combinational logic portions 105 and 110 to scan out latches 155A, 155B, 155C and 155D then to data output pin 140. Each scan in latch 130A, 130B, 130C and 130D has a normal and a test mode input. Each scan out latch 135A, 135B, 135C and 135D has a normal and a test mode output. The latches are xe2x80x9cchainedxe2x80x9d by connecting the test mode inputs together and by connecting the test mode outputs together. During normal operation, the test clocks are held off, allowing the normal inputs on the scan in latches to be clocked through the combinational logic to the normal scan out latch outputs.
If combinational logic circuit 100 contains a very complex structure or if node 115 occurs in a logic path then the test vector that is needed to fully test the circuit or the signals at the node may be prohibitively large. In this case an approach to reducing test vector size is to insert control or observe functions into node 115 as illustrated in FIGS. 3 and 4 and described below. A test point is the node to be controlled or observed.
FIG. 3 is a schematic diagram illustrating the scan latch circuit of FIG. 1 with the addition of a control circuit. In this case a two input AND gate 150 has been inserted into node 115. The first input of AND gate 150 is coupled to control cell 120 and the output to second portion 110. The second input of AND gate 150 is coupled to the output of a two input OR gate 155. The first input of OR gate 155 is coupled to a test data latch 160 and the second input of the OR gate is coupled to an enable pin 165. Applying an enable signal to enable pin 165 causes any special test bit(s) applied to test data latch 160 to be combined with test data being driven onto node 115 by driver cell 120. Thus the special test bit(s) can force a value on test node 115 making diagnosis of the read out data on pin 140 easier and with a test vector of reduced size. FIG. 4 is a schematic diagram illustrating the scan latch circuit of FIG. 1 with the addition of an observe latch. In this case observe latch 170 is coupled to node 115. This allows the pattern on node 115 to directly read, again making diagnosis of the read out data on pin 140 easier and with a test vector of reduced size.
Both the methods illustrated in FIGS. 3 and 4 and described above suffer from the fact that introduction of a control circuit or observe point will change the delay of combinational logic circuit 100. Since logic circuit values must occur at specific times, introduction of significant delay can render diagnosis of read out data problematic. Further, since these control circuits and observe latches are permanently incorporated into combinational logic circuit 100 the normal mode (as opposed to test mode) performance of the circuit is adversely affected as well.
A first aspect of the present invention is a method of inserting a test point into a circuit design, comprising: selecting a node in said circuit design; determining a driver cell of the node; selecting from a file, a replacement cell for the driver cell, the replacement cell having the same function of the driver cell and a test point function; and replacing the driver cell in the circuit design with the replacement cell.
A second aspect of the present invention is a method of inserting a test point into a circuit design, comprising: selecting the test point to be inserted into the circuit design, the circuit design having signal propagation delay limits; determining a driver cell of the test point; selecting from a file, a replacement cell for the driver cell, the replacement cell having the same function of the driver cell and a test point function; determining the delay of the circuit design with the replacement cell; and replacing the driver cell with the replacement cell if the delay of the circuit design with the replacement cell is within the signal propagation delay limits.
A third aspect of the present invention is a method of inserting a test point into a circuit design, comprising: selecting a test point to be inserted into the circuit design, the circuit design having signal propagation delay limits; determining the driver cell of the test point; selecting from a file, all potential replacement cells for the driver cell, the potential replacement cells having the same function of the driver cell and a test point function; determining the delay of the circuit design with each of the potential replacement cells; adding to an accept list those replacement cells where the delay of the circuit design with the potential replacement cell is within the signal propagation delay limits; selecting a replacement cell from the accept list; and replacing the driver cell with the replacement cell.